Intel® X86 Encoder Decoder
Intel® X86 Encoder Decoder User Guide

November 2023


Intel® XED is an acronym for X86 Encoder Decoder. The latter part is pronounced like the (British) English "z".

Intel® X86 Encoder Decoder (Intel® XED) is a software library (and associated headers) written in C for encoding and decoding X86 (IA-32 instruction set and Intel® 64 instruction set) instructions. The decoder takes sequences of 1-15 bytes along with machine mode information and produces a data structure describing the opcode and operands, and flags. The generic encoder takes a similar data structure and produces a sequence of 1 to 15 bytes.

There is another encoder called "enc2" available that is much faster than the generic encoder mentioned above. Rather than using a generic interface, in enc2, instruction encoding is done by calling one of a very large number of functions, passing as arguments the registers and constants that would be used in the assembly language description of the instruction. There are two interfaces to the enc2 encoder: unchecked and checked. The unchecked version is faster and assumes that the arguments passed in are in the correct ranges. The checked version validates that the arguments passed in are in the correct ranges and if that succeeds, it calls the corresponding unchecked version of the function. The checking can be skipped if desired using a runtime setting. The enc2 encoder is available in builds with the "--enc2" option. Due to the large amount of code generated, that build takes longer.

Intel® XED is multi-thread safe.

Intel® XED was designed to be very fast and extensible.

Intel® XED compiles with the following compilers:

  • Microsoft Visual Studio
  • Intel ICL/ICC
  • LLVM/Clang

Intel® XED works with the following operating systems:

  • Linux
  • Microsoft Windows (with and without cygwin)
  • Apple Mac OS X*
  • FreeBSD

The Intel® XED examples (Examples of using Intel® XED) also include binary image readers for Windows PECOFF, ELF, and Mac OS X* MACHO binary file formats for 32b and 64b. These allow Intel® XED to be used as a simple (not symbolic) disassembler. The Intel® XED disassembler supports 3 output formats: Intel, ATT SYSV, and a more detailed internal format describing all resources read and written.

Table of Contents

Building your program using Intel® XED.

This section describes the requirements for compiling with Intel® XED and linking the libxed.a library. It assumes you are building from an Intel® XED kit and not directly from the sources. (See the "install" option in the Intel® XED build manual for information on making kits).

The structure of a Intel® XED kit is as follows:


To use Intel® XED your sources should include the top-most header file: xed-interface.h.

Your compilation statement must include:


where "xed-kit-name" is where you've unpacked the Intel® XED kit.

Your Linux or Mac OS X* link statement must reference the libxed library:

-Lxed-kit-name/lib -lxed

(or link against xed.lib for Windows).

Intel® XED uses base types with the following names: xed_uint8_t, xed_uint16_t, xed_uint32_t, xed_uint64_t xed_int8_t, xed_int16_t, xed_int32_t, and xed_int64_t. Intel® XED also defines a "xed_uint_t" type that is shorthand for "unsigned int".

Please see the section Intel® XED initialization for more information about using Intel® XED, and also the examples in Examples of using Intel® XED.

External Requirements

Intel® XED was designed to have minimal external requirements. Intel® XED makes no system calls. Intel® XED allocates no memory. (The examples are different). The following external functions/symbols are required for linking a program with libxed, with one caveat: The functions fprint and abort and the data object stderr are optional. If users register their own abort handler using xed_register_abort_function () , then fprintf, stderr, and abort are not required and can be stubbed out to satisfy the linker.


  • memcmp
  • memcpy
  • memset
  • strcmp
  • strlen
  • strncat


  • abort
  • fprintf
  • stderr


X86 instructions are 1-15 byte values. They consist of several well-defined components:

  • Prefix bytes.

    • Legacy prefix bytes used for many purposes (described further below).

    • REX prefix byte but only in 64b mode. It has 4 1-bit fields: W, R, X, and B. The W bit modifies the operation width. The R, X and B fields extend the register encodings. The REX byte must be right before the opcode bytes else it is ignored.

    • REX2 prefix, a 2-byte variant of the REX prefix, introduced with Intel® APX extensions (see Intel® APX), adds 16 Extended General Purpose Registers (EGPRs) across the legacy instruction set. It has eight 1-bit fields: M0, R4, X4, B4, W, R3, X3 and B3. R3, X3, B3 and W bits are the same as R, X and B bits in the REX prefix. While R4, X4, and B4 are additional bits used to encode the 32 EGPR registers. M0 bit selects between legacy maps 0 and 1 (1-byte opcodes no escape and 2-byte opcodes escape 0x0F respectively).

    • VEX prefix byte sequence. The VEX prefix is used mostly for AVX1 and AVX2 instructions as well as BMI1/2 instructions and mask operations in Intel® AVX512. The VEX prefix comes in two forms. The 2-byte sequence begins with an 0xC5 byte. The 3-byte sequence begins with an 0xC4 byte.

    • EVEX prefix. The EVEX 4-byte sequence used for encoding Intel® AVX512 instructions and begins with an 0x62 byte. Intel® APX provides an extended version of the prefix, where the semantics of several payload bits are redefined. The extension is essentially used to provide Intel® APX features for legacy instructions that cannot be provided by other prefixes, such as support for the new data destination (see Intel® APX) or status flags update suppression "no flags" which are represented by the ND and NF bits respectively in the third payload byte. Note that the byte following the extended EVEX prefix is always interpreted as the main opcode byte.

    There are somewhat complex rules about which prefixes are allowed, in what order, and in what modes. Intel® XED handles that complexity.

  • 1-3 opcode bytes. When more than one opcode byte is required the leading bytes (called escapes) are either 0x0F, 0x0F 0x38, or 0x0F 0x3A. With VEX and EVEX prefixes, the escape bytes are encoded differently.

  • MODRM byte. Used for addressing memory, refining opcodes, and specifying registers. Optional, but common. It has three fields: the 2-bit "mod", the 3-bit "reg" and 3-bit "r/m" fields.

  • SIB byte. Used for specifying memory addressing, optional. It has three fields: the 2-bit scale, 3-bit index, and 3-bit base.

  • Displacement bytes. Used for specifying memory offsets, optional.
  • Immediate bytes. Optional

Immediates and displacements are usually limited to 4 bytes, but several variants of the MOV instruction can take 8B values. The AMD 3DNow ISA extension uses the immediate field to provide additional opcode information.

The legacy prefix bytes are used for:

  • operand size overrides (1 prefix),
  • address size overrides (1 prefix),
  • atomic locking (1 prefix),
  • default segment overrides (6 prefixes),
  • repeating certain instructions (2 prefixes), and
  • opcode refinement.

There are 11 distinct legacy prefixes. Three of them (operand size and the two repeat prefixes) have different meanings in different contexts. Sometimes they are used for opcode refinement and do not have their default meaning. Less frequently, two of the segment overrides can be used for conditional branch hints.

There are also multiple ways to encode certain instructions, with the same or differing length.

For additional information on the instruction semantics and encodings:

Intel® APX

Intel® Advanced Performance Extensions (Intel® APX) expands the Intel® 64 instruction set architecture with access to more registers and adds various new features that improve general-purpose performance. The extensions are designed to provide efficient performance gains across a variety of workloads without significantly increasing the silicon area or power consumption of the core. The main features of Intel® APX include:

  • Extended GPRs, also known as EGPRs (see Intel® APX Operands)
  • Three-operand instructions with a new data destination (NDD); legacy integer instructions can now use EVEX to encode a dedicated destination register operand – turning them into three-operand instructions and reducing the need for extra register move instructions. The NDD receives the result of the computation, and all other operands (including the original destination operand) become read-only source operands
  • Legacy-promoted instructions that support status flag update suppression "no flags" (NF); an option for the compiler to suppress the status flags writes of common instructions (no CSPAZO flags, such as Parity, Overflow...)
  • Conditional ISA improvements: New conditional load, store and, compare instructions
  • Optimized register state save/restore operations
  • A new 64-bit absolute direct jump instruction
  • Zero Upper (ZU) support for several APX-Promoted instructions, which zero the upper bits of a destination GPR. The destination GPR will get the instruction’s result in bits [OSIZE-1:0] and, if OSIZE < 64b, have its upper bits [63:OSIZE] zeroed

Intel® APX instructions' definition by Intel® XED;


  • Instructions with REX2 prefix are not defined with new iforms or new ISA-SETs
  • The APXLEGACY extension group includes new APX-F instructions


  • Existing (non-APX) EVEX instructions with EGPRs are not defined with new iforms or new ISA-SETs
  • Promoted and new instructions are defined with new iforms using the '_APX' suffix
  • Promoted new data destination instructions with the 'APX_NDD' attribute
  • Promoted no flags instructions with the 'APX_NF' attribute
  • The APXEVEX extension group includes new and promoted APX-F instructions

Intel® AVX10

Intel® Advanced Vector Extensions 10 (Intel® AVX10) establishes a common, converged vector instruction set across all Intel® architectures, incorporating the modern vectorization aspects of Intel® AVX-512.

The Intel® AVX10 architecture introduces several new features and capabilities;

  • Introduces a version-based instruction set enumeration
  • Allows a converged implementation supported on all Intel® CPUs to include all the existing Intel® AVX-512 capabilities such as EVEX encoding, 32 vector registers and 8 32-bit opmask registers at maximum vector length of 256 (Intel® AVX10/256)
  • Allows an implementation to include support for 512-bit vector and 64-bit opmask registers on P-Core CPUs (Intel® AVX10/512) for heavy vector compute applications that can leverage the additional vector length
  • Introduces embedded rounding and Suppress All Exceptions (SAE) control for YMM versions of the instructions

Overview of Intel® XED approach

Intel® XED has two fundamental interfaces: encoding and decoding. Supporting these interfaces are many data structures, but the two starting points are the xed_encoder_request_t and the xed_decoded_inst_t . The xed_decoded_inst_t has more information than the xed_encoder_request_t , but both types are derived from a set of common fields called the xed_operand_values_t.

The output of the decoder, the xed_decoded_inst_t , includes additional information that is not required for encoding but provides more information about the instruction resources.

The common operand fields, used by both the encoder and decoder, hold the operands and the memory addressing information.

The decoder has an operands array that holds the order of the decoded operands. This array indicates whether or not the operands are read or written.

The encoder has an operand array where the encoder user must specify the order of the operands used for encoding.


Intel® XED ISA-SETs can be mapped to one or more CPUID groups, each being mapped to one or more CPUID records. The CPUID record contains information about the register containing the bits to be set, the leaf, subleaf and bit indices. When the leaf and subleaf values are loaded into the EAX and ECX registers, respectively, the CPUID instruction sets the specified bits of the specified register, indicating support for the ISA or the feature, which is often the CPUID name field.

Intel® AVX10 introduced a versioned approach for enumeration that ensures that all Intel® CPUs support the same features and instructions at a given Intel® AVX10 version number. This approach also reduced the required number of CPUID feature flags to be checked to determine feature support. This way, usually, it is only needed to check three fields:

  1. A CPUID feature bit indicating that the Intel® AVX10 ISA is supported
  2. A version number to ensure that the supported version is greater than or equal to the desired version
  3. A vector length bit indicating the maximum supported vector length

Determining whether an ISA-SET is supported by a chip: For ISA-SETs with a single CPUID group, all of its CPUID records must be set in order to be supported by the chip. For ISA-SETs with multiple CPUID groups, at least one CPUID group must be satisfied. In order to match one group, all of its cpuid records must be set. To simplify things, we can transform it into a logical expression -


If one CPUID group is satisfied, the whole expression will be satisfied ("OR" relationship), thus indicating chip support for the ISA. Since the CPUID group itself is an "AND" expression between all of its CPUID records, all CPUID records must be set (satisfied) in order to satisfy the sub-expression.

For instance, the ISA-SET AVX512F_512 has the following CPUIDS groups: The Intel® AVX10 CPUID group with three CPUID records:

  • CPUID name avx10_enabled, leaf 0x7, sub-leaf 0x1, register EDX, bit 19
  • CPUID name avx10_ver1, leaf 0x24, sub-leaf 0x0, register EBX, bits 0 to 7
  • CPUID name avx10_512vl, leaf 0x24, sub-leaf 0x0, register EBX, bit 18

The feature group with a single CPUID record:

  • CPUID name avx512f, leaf 0x7, sub-leaf 0x0, register EBX, bit 16

This means that a chip supports AVX512F_512 ISA if at least one of the two groups has a match. In order to match one CPUID group, all of its records must be set. So either the first group's three CPUID records or the second group's single CPUID record must be set.

To provide further insight on Intel® AVX10 CPUID, let's discuss the first CPUID group of AVX512F_512: The first record ("AVX10 Converged Vector ISA Enable" bit) is indicative of processor support of Intel® AVX10 ISA. The second CPUID record specifies the processor's minimal required Intel® AVX10 version (in this case, AVX10.1). The last CPUID record is the vector length bit indicating the maximum supported VL (512).

For the recommended usage of the Intel® XED CPUID APIS, see Small Examples of using Intel® XED .

Instruction classes

The xed_iclass_enum_t class describes the instruction names. The names are (mostly) taken from the Intel manual, with exceptions only for certain ambiguities. This is what is typically thought of as the instruction mnemonic. Note, Intel® XED does not typically distinguish instructions based on width unless the ISA manuals do so as well. For example, xed_iclass_enum_t's are not suffixed with "w", "l" or "q" typically. There are instructions whose xed_iclass_enum_t ends in a "B" or a "Q" (including all byte operations and certain string operations) and those names are preserved as described in the Intel programmers' reference manuals.

Special Cases

There are many special cases that must be accounted for in attempting to handle all the nuances of the ISA. This is an attempt to explain the nonstandard handling of certain instruction names.

The FAR versions of 3 opcodes (really 6 distinct opcodes) are given the opcode names CALL_FAR, JMP_FAR, and RET_FAR. The AMD documentation lists the far return as RETF. I call that RET_FAR to be consistent with the other far operations.

To distinguish the SSE2 MOVSD instruction from the base string instruction MOVSD, Intel® XED calls the SSE version MOVSD_XMM.

In March 2015, a change was made to certain Intel® XED iclasses to simplify the implementation. The changes are as follows:

  • XED_ICLASS_JRCXZ was split in to three distinct iclasses: XED_ICLASS_JCXZ, XED_ICLASS_JECXZ and XED_ICLASS_JRCXZ.
  • The REP-prefixed (0xF2, 0xF3) string instructions were split in to new iclasses making them distinct from the underlying non-REP-prefixed instructions. For example XED_ICLASS_REP_STOSW is distinct from XED_ICLASS_STOSW. The CMPS{B,W,D,Q} and SCAS{B,W,D,Q} instructions have "REPE_" or "REPNE_" prefixes to correspond to REPE (0xF3) or REPNE (0xF2).
  • LOCK-prefixed (0xF0) atomic read-modify-write memory instructions were split in to separate iclasses that contain the substring "_LOCK". LOCK-prefixed instructions had an attribute XED_ATTRIBUTE_LOCKED. Memory instructions that could have a lock prefix added to them when encoding, have an attribute XED_ATTRIBUTE_LOCKABLE. For example, XED_ICLASS_CMPXCHG16B_LOCK has a lock prefix, but XED_ICLASS_CMPXCHG16B does not have a lock prefix. As always, XCHG is atomic with or without a LOCK prefix as per the rules of the ISA, so XED_ICLASS_XCHG does not have a _LOCK suffix in the xed_iclass_enum_t name.


NOPs are very special. Intel® XED allows for encoding NOPs of 1 to 9 bytes through the use of the XED_ICLASS_NOP (the one-byte nop), and XED_ICLASS_NOP2 ... XED_ICLASS_NOP9. These use the recommended NOP sequences from the Intel® 64 and IA-32 Architectures Software Developers Manual.

The instruction 0x90 is very special in the instruction set because it gets special treatment in 64b mode. In 64b mode, 32b register writes normally zero the upper 32 bits of a 64b register. Not so for 0x90. If it did zero the upper 32 bits, it would not be a NOP.

There are two important NOP categories. XED_CATEGORY_NOP and XED_CATEGORY_WIDENOP. The XED_CATEGORY_NOP applies only to the 0x90 opcode. The WIDENOP category applies to the NOPs in the two-byte table row 0F19...0F1F. The WIDENOPs take MODRM bytes, and optional SIB and displacements.


Intel® XED uses the operand order documented in the Intel Programmers' Reference Manual. In most cases, the first operand is a source and destination (read and written) and the second operand is just a source (read).

For decode requests (xed_decoded_inst_t), the operands array is stored in the xed_inst_t structure once the instruction is decoded. The request's operand order is stored in the xed_encoder_request_t for encode requests.

There are several types of operands:

  • registers (xed_reg_enum_t)
  • branch displacements
  • memory operations (which include base, index, segment and memory displacements)
  • immediates
  • pseudo resources (which are listed in the xed_reg_enum_t)

Each operand has two associated attributes: the R/W action and a visibility. The R/W actions (xed_operand_action_enum_t) indicate whether the operand is read, written or both read-and-written, or conditionally read or written. The visibility attribute (xed_operand_visibility_enum_t) is described in the next subsection.

The memory operation operand is really a pointer to separate fields that hold the memory operation information. The memory operation information is comprised of the following:

  • a segment register
  • a base register
  • an index register
  • a displacement

There are several important things to note:

  • There can only be two memory operations, MEM0 and MEM1.

  • MEM0 could also be an AGEN, which stands for "Address Generation". AGEN is a special operand that uses memory information but does not actually read memory. This is only used for the LEA instruction.

  • There can only be an index and displacement associated with MEM0 (or AGEN).

  • There is just one displacement associated with the common fields. It could be associated with either the AGEN/MEM0 or with a branch or call instruction.

Intel® AVX512 Operands

Intel® AVX512 adds write masking, merging, and zeroing to the instruction set via the EVEX encodings. Write masking, merging, and zeroing are properties of the instruction encoding and are not visible by looking at individual operands. Write masking with merging makes it possible for values of the destination register to live on from prior to the execution of the instruction. Write masking with merging results in an extra register read of the destination operand. In contrast write masking with zeroing always completely overwrites the destination operand, either with values computed by the instruction or with zeros for elements that are "masked off".

For most operands, to learn if the operand reads or writes its associated resource, one can use xed_operand_rw(const xed_operand_t* p). However, because masking, merging and zeroing are properties of the instruction, and not just the operand, use of a different function is required.

To handle this, Intel® XED has a new interface function xed_decoded_inst_operand_action(), which takes a xed_decoded_inst_t pointer and an operand index and indicates how the read/write behavior is modified in the presence of masking with merging or masking with zeroing.

The following list attempts to summarize how the value returned from xed_operand_rw() is internally modified for the 0th operand, except for stores:

  • no masking: no change.
  • masking with zeroing: no change.
  • masking with merging : destination register operands that are nominally "rw" or "w" become "rcw" indicating a read with a conditional write.

Intel® APX Operands

2023 saw the introduction of Intel® Advanced Performance Extensions (Intel® APX), which expands the entire x86 instruction set with access to more registers. Intel® APX doubles the number of general-purpose registers (GPRs) from 16 to 32 (Extended GPRs or EGPRs).

New and promoted APX-F instructions are defined in one of the following Intel® XED extension groups:

  • XED_EXTENSION_APXLEGACY: For new APX-F instructions within the Legacy encoding space
  • XED_EXTENSION_APXEVEX: For new and promoted APX-F instructions within the EVEX encoding space

CCMP and CTEST are two new sets of instructions for conditional CMP and TEST, respectively. These instructions introduce a new 4-bit pseudo-register for "Default Flags Values" called DFV (EVEX.[OF, SF, ZF, CF]).

The register index represents the bits for the default flags, for example, DFV10.index == 10 == 0b1010 -> OF=1, SF=0, ZF=1, CF=0. The DFV pseudo-register should be explicitly defined in an encoder request.

The xed_decoded_inst_get_dfv_reg() API can be used to retrieve a DFV register enumeration from a decoded instruction. The xed_flag_dfv_get_default_flags_values() API can be used to get the default flags values given a DFV register enumeration.

Developers can, however, dynamically disable Intel® APX architecture encoder support using the 'NO_APX' API xed3_operand_set_no_apx(). The xed3_operand_set_must_use_evex() API can also be used for APX promoted instructions in order to force EVEX space upon the encoding request.

Developers wishing to encode No-Flags Intel® APX instructions should set the NF Intel® XED operand. Whereas those wishing to encode SETcc/IMUL with Zero Upper behavior should set the ND Intel® XED operand.

Operand Resource Visibilities

See xed_operand_visibility_enum_t .

There are three basic types of resource visibilities:

  • IMPLICIT (IMPL), and
  • IMPLICIT SUPPRESSED (SUPP) (usually referred to as just "SUPPRESSED").

Explicit are what you think they are: resources that are required for the encoding, and for each explicit resource, and there is a field in the corresponding instruction encoding for each explicit resource. The implicit and suppressed resources are more subtle.

SUPP operands are:

  • not used in picking an encoding,
  • not printed in disassembly,
  • not represented using operand bits in the encoding.

IMPL operands are:

  • used in picking an encoding,
  • expressed in disassembly, and
  • not represented using operand bits in the encoding (like SUPP).

The implicit resources are required for selecting an encoding but do not show up as a specific field in the instruction representation. Implicit resources do show up in a conventional instruction disassembly. In the IA-32 instruction set or Intel64 instruction set, there are many instructions that use EAX or RAX implicitly, for example. Sometimes, the CL or RCX register is implicit. Also, some instructions have an implicit 1 immediate. The opcode you chose fixes your choice of implicit register or immediate.

The suppressed resources are a form of implicit resource, but they are resources not required for encoding. The suppressed operands are not normally displayed in a conventional disassembly. The suppressed operands are emitted by the decoder but are not used when encoding. They are ignored by the encoder. Examples are the stack pointer for PUSH and POP operations. There are many others, like pseudo resources.

The explicit and implicit resources are expressed resources – they show up in disassembly and are required for encoding. The suppressed resources are considered a kind of implicit resources that are not expressed in ATT System V or Intel disassembly formats.

The suppressed operands are always after the implicit and explicit operands in the operand order.

x87 Register stack popping

The Intel® 64 and IA-32 Architectures Software Developers Manual indicates that "FADDP st2", reads st0, st2 writes st2 and pops the x87 stack. The result ends up in st1 after the instruction executes. That is not how Intel® XED represents the operation. Intel® XED will say that "FADDP st2" reads st0 and st2 and writes st2. The output register that Intel® XED provides is essentially "pre pop". The pop occurs afterward, conceptually. The actual result ends up in the st1 register after the stack pop operation. Intel® XED also lists the pseudo resources indicating that a stack pop has occurred. This behavior affects the output register of the following instructions: FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP.

Pseudo Resources

Some instructions reference machine registers or perform interesting operations that we need to represent. For example, the IDTR and GDTR are represented as pseudo resources. Operations that pop the x87 floating point register stack can have an X87POP or X87POP2 "register" to indicate if the x87 register stack is popped once or twice. These are part of the xed_reg_enum_t.

Immediates and Displacements

Using the API functions for setting immediates, memory displacements, and branch displacements. Immediates and Displacements are stored in normal integers internally, but they are stored endian swapped and left justified. The API functions take care of all the endian swapping and positioning so you don't have to worry about that detail.

Immediates and displacements are different things in the ISA. They can be 1, 2, 4 or 8 bytes. Branch displacements (1, 2 or 4 bytes) and Memory displacements (1, 2, 4 or 8 bytes) refer to the signed constants that are used for relative distances or memory "offsets" from a base register (including the instruction pointer) or start of a memory region.

Immediates are signed or unsigned and are used for numerical computations and shift distances. They also hold things like segment selectors for far pointers for certain jump or call instructions.

There is also a second 1B immediate used only for the ENTER instruction.

Intel® XED will try to use the shortest allowed width for a displacement or immediate. You can control Intel® XED's selection of allowed widths using a notion of "legal widths". A "legal width" is a binary number where each bit represents a legal desired width. For example, when you have a valid base register in 32 or 64b addressing, and a displacement is required, your displacement must be either 1 byte or 4 bytes long. This is expressed by OR'ing 1 and 4 together to get 0101 (base 2) or 5 (base 10).

If a four-byte displacement was required, but the value was representable in fewer than four bytes, then the legal width should be set to 0100 (base 2) or 4 (base 10).

API Reference

  • INIT Initialization
  • DEC Decoding instructions
  • ENC Generic API for encoding instructions
  • ENCHL High level API for the generic encoder
  • ENCHLPATCH Patching instructions
  • ENC2 Fast encoder for specific instructions
  • OPERANDS Operand storage fields
  • IFORM Iforms
  • ISASET ISA-sets and chips
  • PRINT Printing (disassembling) instructions
  • REGINTFC Register interface functions
  • FLAGS Flags interface functions
  • AGEN Address generation calculation support
  • ENUM Enumerations
  • Examples Examples

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